library IEEE;
use ieee.std_logic_1164.all;

package package_multi is
	component mux is
	PORT
	(
		a,b,c,d	: IN	STD_LOGIC_VECTOR(7 downto 0);
		sel, cs	: IN 	STD_LOGIC;
		e,f		: OUT	STD_LOGIC_VECTOR(7 downto 0)
	);
	end component;
	
	component referee is
	PORT
	(
		reqa, reqb, rela, relb	: IN	STD_LOGIC;
		acka, ackb, sel, cs		: OUT	STD_LOGIC
	);
	end component;
	
end package_multi;
